1. Field of the Invention
The present invention relates to a semiconductor integrated device.
2. Description of Related Art
FIG. 12 shows a semiconductor memory circuit 1 according to a related art. As shown in FIG. 12, the semiconductor memory circuit 1 includes a cell array area 2, a sense amplifier area 3, and a driver area 4.
The cell array area 2 includes multiple memory cells (CELL1, CELL2, . . . ).
Each memory cell is connected to one of a pair of bit lines D and DB. Each memory cell includes a gate transistor Tr and a cell capacitor Ccell. One of the drain and source of the gate transistor Tr is connected to one of the pair of bit lines D and DB. The other of the drain and source of the gate transistor Tr is connected to the cell capacitor Ccell. A node between the gate transistor Tr and the cell capacitor Ccell serves as a cell node. A terminal of the cell capacitor Ccell on the opposite side of the cell node is connected to an HVDD terminal. The HVDD terminal is supplied with a voltage ½VDD (VDD: power supply voltage). The gate of the gate transistor Tr is connected to a word line WL (WL1, WL2, . . . ).
The sense amplifier area 3 includes a sense amplifier SA1 and a precharge circuit PDLU1.
The sense amplifier SA1 includes PMOS transistors TP11 and TP12 and NMOS transistors TN11 and TN12. The PMOS transistor TP11 and the NMOS transistor TN11 are connected in series between sense amplifier control lines SAP and SAN. The PMOS transistor TP12 and the NMOS transistor TN12 are also connected in series between the sense amplifier control lines SAP and SAN. A connection node A1 between the PMOS transistor TP11 and the NMOS transistor TN11 is connected to the bit line D and the gates of the PMOS transistor TP12 and the NMOS transistor TN12. A connection node A2 between the PMOS transistor TP12 and the NMOS transistor TN12 is connected to the bit line DB and the gates of the PMOS transistor TP11 and the NMOS transistor TN11.
The precharge circuit PDLU1 includes NMOS transistors TN21, TN22, and TN23. The NMOS transistor TN21 is connected between the pair of bit lines D and DB. The NMOS transistor TN22 is connected to the HVDD terminal and the bit line D. The NMOS transistor TN23 is connected to the HVDD terminal and the bit line DB. The gates of the NMOS transistors TN21, TN22, and TN23 are each connected to a precharge control line PDL. For convenience of description, reference symbols “WL”, “SAP”, “SAN”, and “PDL” each represent a line name as well as a name of a signal to be applied to the line.
The driver area 4 includes driver amplifiers AMP1, AMP2, . . . . The driver area 4 further includes driver amplifiers AMP11, AMP12, and AMP20. The amplifiers AMP1, AMP2 . . . apply word signals WL1, WL2, . . . to word lines WL1, WL2, . . . , respectively. A power supply voltage of each of the driver amplifiers AMP1, AMP2, . . . is supplied from a VPP power supply 10. A voltage VPP supplied from the VPP power supply 10 has a potential higher than the power supply voltage VDD.
The driver amplifiers AMP11 and AMP12 apply sense amplifier signals SAP and SAN to the sense amplifier control lines SAP and SAN, respectively, in response to a control signal SE. A power supply voltage of the amplifier AMP11 is supplied from a VDD power supply 20. The VDD power supply 20 supplies a power supply voltage VDD. Note that the driver amplifier AMP12 supplies a ground voltage GND to the sense amplifier control line SAN in response to the control signal SE.
The driver amplifier AMP20 applies a precharge control signal PDL to the precharge control line PDL. A power supply voltage of the driver amplifier AMP20 is supplied from a VPDL power supply 30. A voltage VPDL supplied from the VPDL power supply 30 has a potential higher than the power supply voltage VDD. The reasons for setting the voltage VPDL higher than the power supply voltage VDD are as follows. First, as described above, the precharge voltage of the pair of bit lines D and DB is ½VDD. If the potential of the precharge control signal PDL of high level is set as the power supply voltage VDD, a potential difference between the gate and drain (or source) is about ½VDD. Thus, there is a possibility that the NMOS transistors TN21 to TN23 are not activated rapidly and sufficiently. Such a phenomenon is remarkable particularly when the power supply voltage VDD is further reduced. Therefore, in order to increase the operation speed of the precharge circuit, it is necessary to apply a voltage having a potential higher than that of the power supply voltage VDD (e.g., about VDD+0.5 V) to the gates of the NMOS transistors TN21 to TN23.
Herein, a transistor having a gate oxide film thickness with a breakdown voltage within the range of the normal power supply voltage VDD is referred to as a thin-film transistor, and a transistor having a gate oxide film with a thickness greater than the gate oxide film thickness of the thin-film transistor is referred to as a thick-film transistor. Referring to FIG. 12, in the semiconductor memory circuit 1 of the related art, thick-film transistors are used as the constituent transistors. Each thick-film transistor has a relatively high breakdown voltage characteristic (e.g., 1.5 V or higher). In this case, however, transistors having a larger gate oxide film thickness require a longer channel length, which cases a problem of an increase in layout area of thick-film transistors.
FIG. 13 shows a timing diagram illustrating operation of the semiconductor memory circuit 1. This exemplary embodiment shows the case where the memory cell CELL1 holding high-level information is selected and the information is read out to the bit lines. Additionally, it is assumed that the pair of bit lines D and DB are precharged to the voltage ½VDD.
Referring to FIG. 13, at a time t1, the word signal WL1 rises to the voltage VPP. At this time, the memory cell CELL1 holds the high-level information. Accordingly, the potential of the bit line D slightly increases. At a time t2, the control signal SE becomes high level. Further, the sense amplifier control signal SAP becomes equal to the power supply voltage VDD, and the sense amplifier control signal SAN becomes equal to the ground voltage GND. Thus, the sense amplifier SA1 starts sensing operation and amplifies a potential difference between the pair of bit lines D and DB to the power supply voltage VDD and to the ground voltage GND. Then, the amplified potential difference between the pair of bit lines D and DB is read out to an external circuit.
After that, at a time t3, the word signal WL1 falls to the ground voltage GND. Accordingly, the cell node of the memory cell CELL1 and the bit line D are electrically disconnected from each other. The control signal SE also falls to the ground voltage GND. As a result, the sense amplifier SA1 stops the sensing operation. Then, at a time t4, the precharge control signal PDL rises to the voltage VPDL, and the pair of bit lines D and DB are precharged again to the voltage ½VDD. The semiconductor memory circuit 1 of the related art operates in the manner as described above.
In recent years, there is a demand for higher levels of integration and higher performance of semiconductor integrated devices such as system LSIs. Along with the demand, the miniaturization in fabrication process for semiconductor integrated devices has advanced, and the power supply voltage has been reduced in potential. In such system LSIs, a logic circuit and a memory circuit such as a DRAM coexist. Therefore, a circuit, such as the semiconductor memory circuit 1, and a logic circuit that operates at high speed are integrated into one chip. For this reason, there is a demand for higher speed operation and higher levels of integration of the semiconductor memory circuit 1. Along with the reduction in chip area and the higher speed operation, the gate oxide film of each transistor constituting the semiconductor memory circuit 1 has been reduced in thickness.
In this case, the NMOS transistors TP11, TP12, TN11, and TN12, which constitute the sense amplifier SA1, require a breakdown voltage of about the power supply voltage VDD at a maximum. Accordingly, thin-film transistors having a low breakdown voltage corresponding to the reduced power supply voltage can be used as the MOS transistors TP11, TP12, TN11, and TN12. However, as described above, the high potential VPP is applied to the gate of the gate transistor Tr of each memory cell. It is difficult to reduce the thickness of the gate oxide film of the gate transistor Tr, and thus a thin-film transistor having a relatively thick gate oxide film must be used.
Additionally, the system LSI incorporating the semiconductor memory circuit 1 includes a logic circuit as a peripheral circuit of the semiconductor memory circuit 1 as described above. The logic circuit performs logic processing using data held in the semiconductor memory circuit 1. The logic circuit requires high-speed operation, and thus the most thinned transistors are used in a semiconductor integrated device such as a system LSI. Japanese Unexamined Patent Application Publication No. 2001-15704 (hereinafter referred to as “Patent Document 1”) discloses a technique in which transistors formed of gate oxide films having different thicknesses are used in one semiconductor integrated device, as with the system LSI.